Anti-fuse technology is popular for use in one-time programmable (OTP) memory devices and can be employed to meet various non-volatile memory requirements of many applications while offering low power operation, low cost, and excellent reliability. Known anti-fuse technologies include 2 T anti-fuse bitcells and split channel 1 T (or 1.5 T) anti-fuse bitcells.
The 2 T anti-fuse bitcells include two core N-channel metal oxide semiconductor (NMOS) transistors. For the 2 T anti-fuse bitcells, a program or anti-fuse (AF) transistor is generally coupled in series with a select transistor, with a bitline contact connected to a source region of the select transistor. When a normal supply voltage such as an I/O or core voltage is applied to the gates of the 2 T anti-fuse bitcell, no current is sensed along the bitline. The equivalent circuit for the program transistor is a capacitor. Since there is no current that flows along the bitline, the bitcell is “0” by default. When a large programming voltage is applied along the gate of the AF transistor, gate dielectric breakdown occurs and a resistive path is created. The equivalent circuit for the AF transistor becomes a resistor. A normal supply voltage applied to the gates of the 2 T anti-fuse transistor after programming result in current flow along the bitline and a “1” is sensed. The AF transistors can be programmed at any time. Once programmed, the AF transistors cannot be reverted back to a “0”. Despite utility of the 2 T anti-fuse bitcells, existing 2 T anti-fuse bitcells often exhibit inconsistent and unpredictable gate dielectric breakdown along the gate of the program transistor and gate dielectric breakdown can occur at multiple locations, which leads to a large tail in current distribution. For example, gate dielectric breakdown may occur in the channel of the AF transistor or near a source region adjacent to the AF transistor, thereby creating a bimodal distribution and raising reading error and reliability concerns.
The split channel 1 T anti-fuse bitcells include an AF transistor with a thin (core) gate dielectric layer and an AF gate disposed thereover, and a select transistor with a thick (I/O) gate dielectric layer and a select gate disposed thereover. The AF transistor and the select transistor are disposed adjacent to each other in series. A bitline contact is connected to a source region adjacent to the select transistor. The thin gate dielectric layer of the AF transistor is thinner than the thick gate dielectric layer of the select transistor. When a normal supply voltage such as an I/O or core voltage is applied to the gates, no current is sensed along the bitline. The equivalent circuit is a capacitor. Since there is no current that flows along the bitline, the bitcell is “0” by default. When a large programming voltage is applied along the AF gate, gate dielectric breakdown occurs and a resistive path is created through the thin gate dielectric layer of the AF transistor. The equivalent circuit for the thin gate is a resistor. Due to the thickness gradient, gate oxide breakdown occurs at the weakest link, which is the junction of the thick gate dielectric layer and the thin gate dielectric layer. Despite enhanced controllability of gate dielectric breakdown with the split channel 1 T anti-fuse bitcells, programming disturbances (e.g., undesired dielectric breakdown within anti-fuse dielectric layers that are not intended to be subject to the programming voltage) still occur during programming of other AF bitcells in the integrated circuit.
Accordingly, it is desirable to provide integrated circuits that have an anti-fuse device that is more robust than existing anti-fuse configurations, with gate dielectric breakdown more predictably controlled at specific locations within the anti-fuse transistors. Further, it is desirable to provide methods of forming the integrated circuits that have the anti-fuse configuration within existing fabrication schemes without the need for added masking and patterning techniques. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.